1. Field of the Invention
The present invention generally relates to the art of microelectronic circuit fabrication, and more specifically to a computer implemented method for estimating a fabrication yield for a semiconductor integrated circuit including memory blocks with redundant rows and/or columns.
2. Description of the Related Art
For faster performance, modern microprocessors devote substantial area to on-chip cache memory. From microprocessor generation to generation, the trend is to include larger caches, larger both in the sense of transistor and bit count, and in fraction of mask area.
Because of their large size and symmetric form, the features defining cache are laid out more densely than in random logic, sensitizing them to smaller defects. As a result, caches have emerged as an important factor in determining overall chip yield.
Following the precedent of memory chip manufacturers, some microprocessors now include on-chip repair schemes or redundancy for their caches. A redundancy scheme includes one or more redundant rows and/or columns. If, during testing, a cache is determined to have a defect such as a failed bit or row, the defect is repaired by remapping the failed bit or row to one of the redundant rows. This can be accomplished by altering the cache itself, such as by blowing fuses, or by software in the startup routine which detects a failure and performs the remapping.
Numerous variables must be considered and traded off in the design of a new microprocessor which includes a cache memory. The goal is to produce the best possible product consistent with a high production or fabrication yield, and thereby at lowest fabrication cost. Fabrication yield is the percentage of integrated circuit dies on a wafer that are sufficiently free of defects such that they can be further processed into integrated circuit chips for sale.
Cache redundancy schemes increase yield by enabling die with certain defects to be repaired. However, redundant rows and columns take up valuable space on chips which could otherwise be used for more microprocessor logic or cache memory. For this reason, it is important to provide an estimate of the yield increase which can be provided by a given redundancy scheme, and also to determine which redundancy scheme can produce the highest return for the additional test, manufacturing and yield investment.
Methods have been proposed in the prior art for estimating the yield of a memory with a redundancy scheme. Articles entitled "Improved Yield Models for Fault-Tolerant Memory Chips", by C. Stapper, IEEE Transactions on Computers, Vol. 42, No. 7, July 1993, and "Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product", by C. Stapper et al, IBM Journal of Research and Development, Vol. 24, No. 3, May 1980 disclose methods using a multiple negative binomial model to estimate yield after repair for a particular redundancy scheme.
Newer microprocessors tend to have larger cache memories than earlier microprocessors. In addition, the architecture of the newer cache memories tends to be different from that of the earlier memories. Typically, larger cache memories will be organized into more blocks or "macros" than earlier memories.
The Stapper methods are capable of estimating the yield increase provided by a redundancy scheme for a cache memory having a given architecture based on data obtained from an existing cache memory having the same architecture. However, Stapper's methods do not include provisions for extrapolating or "scaling" yield estimates from one type of memory architecture to another.